Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand has increased for electronic systems to be faster, have greater data capacity, and consume less power, semiconductor memories that may be accessed faster, store more data, and use less power have been continually developed to meet the changing needs. Part of the development includes creating new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems.
Semiconductor memories are generally controlled by providing the memories with command signals, address signals, clock signals. The various signals may be provided by a memory controller, for example. The command signals may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a write operation to store data to the memory. The data may be provided between the controller and memories with known timing relative to receipt by the memory of an associated command. The known timing is typically defined by latency information. The latency information may be defined by numbers of clock cycles of system clock signals CK and CKF.
With newly developed memories, the memories may be provided with system clock signals that are used for timing the command signals and address signals, for example, and further provided with data clock signals that are used for timing the read data provided by the memory and for timing the write data provided to the memory. The memories may also provide clock signals to the controller for timing the provision of data provided to the controller.
The timing of various memory commands provided by the controller and received by the memories may be used to control performance of the memories, including the timing of when clock signals are provided, when data is provided, etc. Limitations on the timing of the various memory commands relative to one another may result in less desirable performance by the memories. As such, it may be desirable to have memory commands with flexible timing to provide desirable memory performance.